ARM DACR basics

Programming 2016. 7. 13. 12:59
이게 thread_info 의 cpu_domain 필드의 값인가?

01struct thread_info {
02    unsigned long       flags;              /* low level flags */
03    int         preempt_count;          /* 0 => preemptable, <0 => bug */
04    mm_segment_t        addr_limit;     /* address limit */
05    struct task_struct  *task;              /* main task structure */
06    struct exec_domain  *exec_domain;       /* execution domain */
07    __u32           cpu;                /* cpu */
08    __u32           cpu_domain;         /* cpu domain */
09    struct cpu_context_save cpu_context;        /* cpu context */
10    __u32           syscall;            /* syscall number */
11    __u8            used_cp[16];            /* thread used copro */
12    unsigned long       tp_value[2];        /* TLS registers */
13    union fp_state      fpstate __attribute__((aligned(8)));
14    union vfp_state     vfpstate;

5.5.1. Domains

A domain is a collection of memory regions. The ARM architecture supports 16 domains. Domains provide support for multi-user operating systems. All regions of memory have an associated domain.

A domain is the primary access control mechanism for a region of memory and defines the conditions in which an access can proceed. The domain determines whether:

  • access permissions are used to qualify the access

  • access is unconditionally permitted to proceed

  • access is unconditionally aborted.

In the latter two cases, the access permission attributes are ignored.

Each page table entry and TLB entry contains a field that specifies which domain the entry is in. Access to each domain is controlled by a 2-bit field in the Domain Access Control Register, CP15 c3. Each field enables very quick access to be achieved to an entire domain, so that whole memory areas can be efficiently swapped in and out of virtual memory. Two kinds of domain access are supported:


Clients are users of domains in that they execute programs and access data. They are guarded by the access permissions of the TLB entries for that domain.

A client is a domain user, and each access must be checked against the access permission settings for each memory block and the system protection bit, the S bit, and the ROM protection bit, the R bit, in CP15 Control Register c1.Table 5.1 shows the access permissions.


Managers control the behavior of the domain, the current sections and pages in the domain, and the domain access. They are not guarded by the access permissions for TLB entries in that domain.

Because a manager controls the domain behavior, each access has only to be checked to be a manager of the domain.

One program can be a client of some domains, and a manager of some other domains, and have no access to the remaining domains. This enables flexible memory protection for programs that access different memory resources.

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